This disclosure relates to memory address translation.
A data processing apparatus may provide each running program or peripheral device with access to a virtual address space defined by virtual memory addresses. Each program or device sees its own virtual address space which contains instructions and data for use by that program or device. Amongst other established advantages, the use of virtual addressing allows the operating system to control memory access by inhibiting one program from accessing or corrupting information used by another program.
When an access is required to a virtual memory address, it is first necessary to translate the virtual memory address to a physical memory address so that the required information can be obtained from or written to the physical memory or a physical memory cache.
A cache known as a translation lookaside buffer (TLB) may be used as part of the address translation process. The TLB stores recently or commonly used translations between virtual and physical memory addresses, on a fixed size page-by-page basis. So, as a first step in an address translation process, a TLB may be consulted to detect whether the TLB already contains the required address translation. If not, then a more involved translation process may be used, for example involving consulting so-called page tables holding address translation information, typically resulting in the TLB being populated with the required translation.